Semiconductor device including polysilicon structures and method of making

ABSTRACT

A semiconductor device includes a first polysilicon structure, wherein the first polysilicon structure has a first grain size. The semiconductor device further includes a first barrier layer over the first polysilicon structure, wherein the first barrier layer has a non-uniform thickness. The semiconductor device includes a second polysilicon structure over the first barrier layer, wherein the second polysilicon structure has a second grain size different from the first grain size.

RELATED APPLICATION

This application is a continuation of U.S. application Ser. No.17/380,340, filed Jul. 20, 2021, which is a continuation of U.S.application Ser. No. 16/773,640, filed Jan. 27, 2020, now U.S. Pat. No.11,094,584, issued Aug. 17, 2021, which is a divisional of U.S.application Ser. No. 15/685,220, filed Aug. 24, 2017, now U.S. Pat. No.10,553,476, issued Feb. 4, 2020, which claims the benefit of U.S.Provisional Application No. 62/511, 473, filed May 26, 2017, which arehereby incorporated by reference in their entireties.

BACKGROUND

Polysilicon structures, such as transistor gate structures andresistors, are used in a variety of devices. During manufacturing of acomplete semiconductor device, the polysilicon structure is subjected tonumerous thermal processes. The thermal processes increase a grain sizewithin the polysilicon structures.

Doping of the polysilicon structures is used to control resistance foran electrical signal passing through the polysilicon structure. Thedopants migrate along grain boundaries in the polysilicon structures.The amount of resistance in the polysilicon structures is a factor inpower consumption of a semiconductor device including the polysiliconstructures.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 is a flowchart of a method of forming a semiconductor deviceaccording to some embodiments.

FIGS. 2A-2E are cross-sectional views of a semiconductor device atvarious stages of manufacture according to some embodiments.

FIG. 3 is a cross-sectional view of a gate structure according to someembodiments.

FIG. 4 is a flowchart of a method of forming polysilicon structuresaccording to some embodiments.

FIGS. 5A-5D are cross-sectional views of polysilicon structures atvarious stages of manufacture according to some embodiments.

FIG. 6 is a cross-sectional view of a gate structure according to someembodiments.

FIG. 7 is a cross-sectional view of a gate structure including dopantsaccording to some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components, values, operations, materials,arrangements, or the like, are described below to simplify the presentdisclosure. These are, of course, merely examples and are not intendedto be limiting. Other components, values, operations, materials,arrangements, or the like, are contemplated. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

Polysilicon structures are used in a variety of semiconductor devices,such as memory devices, logic devices, and other suitable devices.Providing stable and predictable resistance within polysiliconstructures helps to increase stability of an operating voltage of thesemiconductor device and increase predictability of power consumption.As device sizes shrink, an importance of battery life for semiconductordevices, such as portable devices for the internet of things (TOT),increases. Accurate prediction of power consumption by the semiconductordevice helps to reduce overdesign of batteries and facilitate acontinued decrease in device sizes. Semiconductor devices like staticrandom access memory (SRAM) are also affected by a stability of anoperating voltage across different polysilicon structures. For example,an increased resistance in a polysilicon gate structure will, in someinstances, decrease a speed of a signal through the SRAM to a point thatan incorrect value is read out of the SRAM, i.e., a “0” is read insteadof a “1” and vice versa.

Conductivity of the polysilicon structures is determined in part basedon a dopant concentration in the polysilicon structures. As dopantconcentration increases, conductivity also increases. Dopants inpolysilicon structures migrate along grain boundaries of the polysiliconstructures. In addition, the decrease in device size results in moredensely located devices and an increase in a number of thermal processesperformed during manufacturing the semiconductor device. These thermalprocesses cause grain sizes in the polysilicon structures to increase.The increased grain sizes reduce migration paths for dopants within thepolysilicon structure, which in turn reduces a number of conductivepaths through the polysilicon structure and increases resistance of thepolysilicon structure. Further, the increase in grain sizes is noteasily controlled within a continuous polysilicon material. Thedifficulty in controlling grain size growth within a continuouspolysilicon material decreases a level of predictability of theresistance of different polysilicon structures within a samesemiconductor device.

In order to control a size of grains within polysilicon structures, atleast one barrier layer is used to reduce or prevent grain growth. Grainboundaries which contact the barrier layer cease expanding, whichinhibits increases in grain size within the polysilicon structures. As aresult, resistance of the polysilicon structures within a semiconductordevice is lower and more uniform in comparison with polysiliconstructures which do not include the at least one barrier layer. Theincreased uniformity of resistance of the polysilicon structures helpswith the design of memory devices by reducing a risk of memory errorsresulting from signal delays cause by unpredictable resistance values.The lower and more uniform resistance also reduces an amount ofoverdesign for batteries in portable devices to help facilitatereduction in overall device size.

FIG. 1 is a flowchart of a method 100 of making a semiconductor deviceaccording to some embodiments. Method 100 includes operation 110 inwhich a polysilicon layer is deposited on a substrate. The polysiliconlayer is deposited to thickness ranging from 10 nanometers (nm) to 400nm. The thickness of the poly silicon layer is determined based on atechnology node of a semiconductor device in which the polysiliconstructures are included. As a size of the technology node decreases, thethickness of the polysilicon layer decreases. In some embodiments, thesemiconductor device is manufactured using a technology node such asN90, N55, N40 or another suitable technology node.

In some embodiments, the polysilicon layer is deposited over adielectric layer, such as an interfacial layer, a gate dielectric layer,an isolation feature or another suitable dielectric layer. In someembodiments, the polysilicon layer is deposited using a chemical vapordeposition (CVD), such as a low-pressure CVD (LPCVD). In someembodiments, the polysilicon layer is deposited using a silane (SiH₄)precursor.

In some embodiments, the polysilicon layer is deposited at a temperatureranging from about 450° C. to about 620° C. A deposition temperature ofthe polysilicon layer impacts a grain size of the polysilicon layerdeposited. The grain size of the polysilicon layer in turn impacts anumber of possible conductive paths within the polysilicon structures.As the deposition temperature increases, a size of the grains in thepolysilicon layer increases.

In optional operation 120, the polysilicon layer is doped. In someembodiments, operation 120 is performed simultaneously with operation110, i.e., an in-situ doping during deposition of the polysilicon layer.In-situ doping includes incorporating a dopant material, such asarsenic, phosphorous, boron or another suitable dopant, into the flow ofmaterial, e.g., silane, used to deposit the polysilicon layer.

In some embodiments, operation 120 includes an ion implantation process.In some embodiments, the ion implantation occurs at an energy rangingfrom about 30 kilo electronvolts (KeV) to 75 KeV. As the energy of theimplantation process increases a depth of the dopant implanted into thepolysilicon layer increases. Thus, an energy of the implantation processis determined in part based on a thickness of the polysilicon layer.Further, a higher implantation energy damages a crystal structure of thepoly silicon layer which increases a resistance of the polysiliconlayer. A target resistance of the polysilicon structures is also afactor in selecting the implantation energy. In some embodiments, thedosage of the dopant implanted ranges from about 5E14 atoms/cm² to about1E16 atoms/cm². As a dosage increases resistance in the polysiliconlayer decreases.

In some embodiments, operation 120 includes depositing a layer of dopantmaterial on the polysilicon layer and annealing the semiconductor deviceto drive the dopants into the polysilicon layer. In some embodiments,operation 120 is omitted and a doping process is performed afteroperation 150 of method 100.

In operation 130, the polysilicon layer is patterned to define locationsof polysilicon structures. In some embodiments, the patterning processincludes depositing a photoresist over the polysilicon layer. Alithography process is then used to pattern the photoresist. The patternis then developed to remove portions of the photoresist corresponding toportions of the polysilicon layer to be removed. The polysilicon layeris then etched using the patterned photoresist as a mask. In someembodiments, the etching process includes a wet etching process. In someembodiments, the wet etchant includes nitric acid, hydrochloric acid oranother suitable etchant. In some embodiments, the etching processincludes a dry etching process. In some embodiments, the dry etchantincludes chlorine-containing gas, fluorine-containing gas or anothersuitable etchant. In some embodiments, the photoresist is removed duringthe etching process. In some embodiments, an ashing process is used toremove residual photoresist following the etching process.

In some embodiments, the polysilicon layer is patterned using a laserdrilling process or another suitable material removal process.Following, the patterning process, one or more polysilicon structuresare defined on the substrate. In some embodiments, at least onepolysilicon structure is over an n-doped region of the substrate andanother polysilicon structure is over a p-doped region of the substrate.

In operation 140, a barrier layer is formed over the polysiliconstructures. A thickness of the barrier layer near a center of eachpolysilicon structure is less than a thickness of the barrier layer nearan edge of the polysilicon structure. The increased thickness of thebarrier layer near the edge of the polysilicon structure is a result offormation of the barrier layer at the sidewalls of the polysiliconstructure as well as a top surface of the polysilicon structure. Theformation of the barrier layer at the sidewalls of the polysiliconstructure is result of the patterning of the polysilicon layer prior toformation of the barrier structures. The formation of the barrierstructures acts on both the top surface of the patterned polysiliconstructure as well as the sidewalls of the patterned silicon structureresulting in increased thickness of the barrier layer near the sidewallsof the patterned polysilicon layer. In some embodiments, a thickness ofthe barrier layer near a center of the polysilicon structure ranges fromabout 0.3 nm to about 1.5 nm. In some embodiments, a thickness of thebarrier layer near an edge of the polysilicon structure ranges fromabout 2 nm to about 10 nm. As a thickness of the barrier layerincreases, a resistance in the polysilicon structure increases. If athickness of the barrier layer is too small, the barrier layer will notbe able to inhibit increases in grain size in the polysilicon material.In some embodiments, a thickness of the barrier layer over the centerregion of the polysilicon structure is substantially uniform and thethickness increases in a gradient a distance D from the edge of the polysilicon structure. In some embodiments, the distance D ranges from about2 nm to about 3 nm from the edge of the polysilicon structure. As thedistance D increases the resistance of the polysilicon structureincreases. The distance D is determined by a rate of formation of thebarrier layer at the edge of the poly silicon structure.

The barrier layer has a dielectric constant ranging from about 2 toabout 13. In some embodiments, the barrier layer includes silicon oxide,silicon nitride, silicon oxynitride, silicon carbide or another suitablebarrier material. In some embodiments, the silicon oxynitride isrepresented by SiO_(a)N_(b), where a ratio of a/b ranges from about 0.1to about 10. In some embodiments, the silicon nitride is represented bySi_(x)N_(y), where a ratio of x/y ranges from about 0.1 to about 10.

In some embodiments, the barrier layer is formed by physical vapordeposition (PVD), CVD, ALD or another suitable deposition process. Insome embodiments, the barrier layer is formed by exposing thepolysilicon structure to an ambient environment containing oxygen. Insome embodiments, an oxygen-containing gas is blown across the polysilicon structures. A thickness of the barrier layer is determined by aduration of the formation process. For example, as a length of time thatthe polysilicon is exposed to the ambient environment containing oxygenincreases, a thickness of the barrier increases. In some embodiments, atemperature of the barrier layer formation process ranges from about 25°C. to about 1100° C. A higher temperature increases a size of grains inthe polysilicon structure. In some embodiments,

In some embodiments, the barrier layer is doped. In some embodiments, aspecies of dopant in the barrier layer is a same species as that in thepolysilicon structures. In some embodiments, a species of dopant in thebarrier layer is different from a species of dopant in the polysiliconstructures. In some embodiments, the barrier is doped by an in-situprocess, an ion implantation process, an anneal process (which drivesdopants from the polysilicon structures into the barrier layer) oranother suitable process.

In operation 150, whether the Height of the polysilicon structuresincluding the barrier layer satisfies a threshold value is determined.The height is measured form a top surface of the substrate in adirection perpendicular to the top surface of the substrate. Thethreshold value is determined based on a technology node of thesemiconductor device. In some embodiments, the threshold value rangesfrom about 20 nm to 400 nm. As a size of the technology node decreases,the threshold value decreases. In some embodiments, the threshold valueis larger than a desired final height of the polysilicon structureincluding the barrier layer to account for a subsequent material removalprocess, such as a planarization process.

If the height fails to satisfy the threshold value, then method 100returns to operation 110 and an additional polysilicon layer isdeposited. The sequence of operations 110-140 are repeated until theheight satisfies the threshold value. In some embodiments, operation 140is omitted in a final repetition of operations 110-140. In someembodiments where operation 140 is not omitted in the final repetition,a top-most barrier layer is removed using a material removal process,such as etching, planarization, or another suitable material removalprocess.

If the height satisfies the threshold value, then method 100 proceeds tooperation 160 in which processes for completion of a gate structure or aresistor structure are completed. A gate structure is formed where thepolysilicon structure is over a conductive region of the substrate. Aresistor structure is formed where the polysilicon structure is over anon-conductive region of the substrate, such as an isolation feature.The subsequent processes include formation of spacers; formation ofsource/drain features; formation of lightly doped drain (LDD) features;formation of an inter-layer dielectric (ILD); formation of contactplugs; formation of interconnect structures; or other suitableprocesses.

In some embodiments, method 100 includes additional operations. Forexample, in some embodiments, method 100 includes an operation forremoving a top most barrier layer over a top most polysilicon structure.In some embodiments, an order of operations is adjusted. For example, insome embodiments, operation 140 is performed prior to operation 130. Insome embodiments, at least one operation of method 100 is omitted. Forexample, in some embodiments, operation 120 is omitted and a singledoping process is performed during operation 160.

FIGS. 2A-2E are cross-sectional view of a semiconductor device atvarious stages of manufacturing according to some embodiments. Samereference numbers correspond to same elements in each of the Figures.FIG. 2A is a cross-sectional view of a semiconductor device 200following deposition of polysilicon layer 220 according to someembodiments. Polysilicon layer 220 is on substrate 210. In someembodiments, a dielectric layer, such as an interfacial layer, a gatedielectric, an isolation structure or another suitable dielectric layer,is between at least a portion of polysilicon layer 220 and substrate210. A thickness of polysilicon layer 220 ranges from about 10 nm toabout 400 nm. In some embodiments, polysilicon layer 220 is doped.

FIG. 2B is a cross-sectional view of semiconductor device 200′ followingpatterning of the poly silicon layer according to some embodiments. Incomparison with semiconductor device 200, semiconductor device 200′includes polysilicon structures 220 a and 220 b. Polysilicon structure220 a is part of a gate structure 250 a. Polysilicon structure 220 b ispart of a gate structure 250 b. Poly silicon structures 220 a and 220 bare formed by removing portions of polysilicon layer 220, such as byusing a lithography and etching process.

In some embodiments, a portion of substrate 210 below polysiliconstructure 220 a has a different dopant type from a portion of substrate210 below polysilicon structure 220 b. In some embodiments, an isolationfeature, such as a shallow trench isolation (STI), is in substrate 210below polysilicon structure 220 a or polysilicon structure 220 b.Semiconductor device 200′ includes two polysilicon structures 220 a and220 b. In some embodiments, semiconductor device 200′ includes more thantwo polysilicon structures.

FIG. 2C is a cross-sectional view of semiconductor device 200″ followingformation of barrier layers 230 a and 230 b according to someembodiments. In comparison with semiconductor device 200′, semiconductordevice 200″ includes barrier layer 230 a over polysilicon structure 220a; and barrier layer 230 b over polysilicon structure 220 b. Barrierlayers 230 a and 230 b independently have a dielectric constant rangingfrom about 2 to about 13. In some embodiments, barrier layers 230 a and230 b include silicon oxide, silicon nitride, silicon oxynitride,silicon carbide or another suitable barrier material. In someembodiments, barrier layer 230 a includes a same material as barrierlayer 230 b. In some embodiments, barrier layer 230 a includes adifferent material from barrier layer 230 b.

A thickness of each of barrier layers 230 a and 230 b near a center of acorresponding polysilicon structure 220 a or 220 b is less than athickness of the barrier layer 230 a or 230 b near an edge of thecorresponding polysilicon structure 220 a or 220 b. In some embodiments,a thickness of the barrier layers 230 a and 230 b near a center of thecorresponding polysilicon structure 220 a or 220 b ranges from about 0.3nm to about 1.5 nm. In some embodiments, a thickness of the barrierlayers 230 a and 230 b near an edge of the corresponding polysiliconstructure 220 a and 220 b ranges from about 2 nm to about 10 nm. As athickness of the barrier layer increases, a resistance in thepolysilicon structure increases. If a thickness of the barrier layer istoo small, the barrier layer will not be able to inhibit increases ingrain size in the polysilicon material. In some embodiments, a thicknessof the barrier layers 230 a and 230 b over the center region of thecorresponding polysilicon structure 220 a or 220 b is substantiallyuniform and the thickness increases in a gradient a distance D towardthe edge of the corresponding polysilicon structure 220 a or 220 b. Insome embodiments, the distance D ranges from about 2 nm to about 3 nmfrom the edge of the polysilicon structure 220 a or 220 b. As thedistance D increases the resistance of the polysilicon structure 220 aor 220 b increases.

In some embodiments, a thickness profile of barrier layer 230 a matchesa thickness profile of barrier layer 230 b. In some embodiments, thethickness profile of barrier layer 230 a is different from the thicknessprofile of barrier layer 230 b. For examples, in some embodiments, acenter thickness of both barrier layers 230 a and 230 b is the same, buta thickness of barrier layer 230 a near an edge of polysilicon structure220 a is different from a thickness of barrier layer 230 b near an edgeof polysilicon structure 220 b.

FIG. 2D is a cross-sectional view of semiconductor device 200* afterdeposition of a second polysilicon layer 240 according to someembodiments. In comparison with semiconductor device 200″, semiconductordevice 200* includes polysilicon layer 240 over portions of substrate210 exposed by polysilicon structures 220 a and 220 b. Polysilicon layer240 is also over barrier layers 230 a and 230 b. A thickness ofpolysilicon layer 240 ranges from about 10 nm to about 400 nm. In someembodiments, polysilicon layer 240 has a same thickness as polysiliconlayer 220. In some embodiments, polysilicon layer 240 has a differentthickness from polysilicon layer 220. In some embodiments, polysiliconlayer 240 is deposited using a same process as that used for polysiliconlayer 220. In some embodiments, polysilicon layer 240 is deposited usinga different process from that used for polysilicon layer 220. In someembodiments, polysilicon layer 240 is doped.

FIG. 2E is a cross-sectional view of semiconductor device 200{circumflexover ( )} following patterning of the polysilicon layer 240 according tosome embodiments. In comparison with semiconductor device 200*,semiconductor device 200{circumflex over ( )} includes polysiliconstructure 240 a over barrier layer 230; and polysilicon structure 240 bover barrier layer 230 b. Polysilicon structure 240 a is part of a gatestructure 250 a. Polysilicon structure 240 b is part of a gate structure250 b. Polysilicon structures 240 a and 240 b are formed by removingportions of polysilicon layer 240, such as by using a lithography andetching process. In some embodiments, the removal process for formingpolysilicon structures 240 a and 240 b is a same as the removal processto form polysilicon structures 220 a and 220 b. In some embodiments, theremoval process for forming polysilicon structures 240 a and 240 b isdifferent from the removal process to form polysilicon structures 220 aand 220 b.

FIG. 3 is a cross-sectional view of a gate structure 300 according tosome embodiments. Gate structure 300 includes polysilicon structures 310a, 310 b and 310 c, collectively referred to as polysilicon structures310. Gate structure 300 further includes barrier layers 320 a and 320 b,collectively referred to as barrier layers 320. While gate structure 300includes two barrier layers, in some embodiments, a number of barrierlayers in gate structure 300 ranges from 1 to about 10. Barrier layers320 independently have a dielectric constant ranging from about 2 toabout 13. Barrier layer 320 a is between polysilicon structure 310 a andpolysilicon structure 310 b. Barrier layer 320 b is between polysiliconstructure 310 b and polysilicon structure 310 c. A grain size inpolysilicon structure 310 a is greater than a grain size in polysiliconstructure 310 b. A grain size in polysilicon structure 310 b is greaterthan a grain size in polysilicon structure 310 c. The larger grain sizesare the result of the lower polysilicon structures 310 being subjectedto a greater number of thermal processes.

A thickness Hc of the barrier layers 320 near a center of polysiliconstructures 310 is less than a thickness He of the barrier layers 320near an edge of the polysilicon structures 310. In some embodiments,thickness Hc of the barrier layers 320 near a center of the polysiliconstructures 310 independently ranges from about 0.3nm to about 1.5 nm. Insome embodiments, thickness He of the barrier layers 320 near an edge ofthe polysilicon structures 310 independently ranges from about 2 nm toabout 10 nm. In some embodiments, a thickness profile of barrier layer320 a is a same as a thickness profile of barrier layer 320 b. In someembodiments, the thickness profile of barrier layer 320 a is differentfrom the thickness profile of barrier layer 320 b. As a thickness of thebarrier layers 320 increase, a resistance in the gate structure 300increases. If a thickness of the barrier layers 320 is too small, thebarrier layers will not be able to inhibit increases in grain size inthe polysilicon structures 310. In some embodiments, a thickness of thebarrier layers 320 over the center region of the polysilicon structures310 is substantially uniform and the thickness increases in a gradient adistance D from the edge of the polysilicon structures 310. In someembodiments, the distance D independently ranges for each of the barrierlayers 320 from about 2 nm to about 3 nm from the edge of the polysilicon structure. As the distance D increases the resistance of thegate structure 300 increases.

A thickness Hp of polysilicon structures 310 independently ranges fromabout 10 nm to about 400 nm. In some embodiments, at least one of polysilicon structures 310 is doped. The thickness Hp of polysiliconstructures 310 is determined based on a technology node of thesemiconductor device containing gate structure 300. A gate height Hg ofgate structure 300 ranges from about 15 nm to about 410 nm. The gateheight Hg of gate structure 300 is determined based on a technology nodeof the semiconductor device containing gate structure 300.

FIG. 4 is a flowchart of a method 400 of making a semiconductor deviceaccording to some embodiments. In comparison with method 100, method 400includes a patterning operation following the polysilicon layers andbarrier layers satisfying the height threshold. The single patterningprocess helps to reduce complexity of method 400 in comparison withother approaches. Also, the barrier layers formed in method 400 have asubstantially constant thickness because the formation process act onthe top surface of the polysilicon layer with minimal actions onsidewalls of the poly silicon.

In operation 410, a polysilicon layer is deposited on the substrate.Operation 410 is similar to operation 110; and the above discussion ofoperation 110 is applicable to operation 410. In some embodiments, thepolysilicon layer is deposited on a dielectric layer, such as aninterfacial layer, a gate dielectric layer, an isolation structure oranother suitable dielectric layer.

In optional operation 420, the polysilicon layer is doped. Operation 420is similar to operation 120; and the above discussion of operation 120is applicable to operation 420. In some embodiments, operation 420 isomitted and a single doping process is performed in operation 460.

In operation 430, a barrier layer is formed over the polysilicon layer.In comparison with operation 140, operation 430 is performed on a polysilicon layer not on a patterned polysilicon structure. As a result, theprocess for forming the barrier layer acts on the top surface of thepolysilicon layer and on the sidewalls of the polysilicon layer at theedge of the substrate. The formation process acting primarily on the topsurface of the polysilicon layer means that the thickness of the barrierlayer formed by operation 430 is substantially constant. Variations inthe thickness result from process gradients and imperfections in crystalstructure of the polysilicon layer, in some instances; however, thethickness of the barrier layer is substantially constant. The formationprocesses for forming the barrier layer in operation 430 are similar tothe processes for forming the barrier layer in operation 140; and thediscussion is not repeated here for the sake of brevity.

In operation 440, the height of the polysilicon layer and barrier layeris compared to a threshold value. The determination of the thresholdvalue is based on the technology node of the semiconductor device. Thediscussion of operation 150 above is applicable to operation 440 and isnot repeated here for the sake of brevity. If the height fails tosatisfy the threshold value, then method 400 returns to operation 410.Similar to method 100, in some embodiments of method 400, formation ofthe barrier layer over a top most polysilicon layer is omitted. In someembodiments, method 400 further includes an operation for removing atop-most barrier layer over a top-most polysilicon layer.

If the height satisfies the threshold value, method 400 proceeds tooperation 450. In operation 450, the polysilicon layers and barrierlayers are patterned to define a location of gate structures or resistorstructures. Gate structures are located over conductive regions of thesubstrate. Resistor structures are located over non-conductive regions,such as isolation structures, of the substrate.

In some embodiments, the patterning process is performed using aphotoresist as a mask for an etching process. A discussion of the use ofa photoresist to create a mask for etching is provided above in withrespect to operation 130. The description is not repeated for the sakeof brevity. An etching process for operation 450 is either a wet etchingprocess or a dry etching process. In some embodiments, differentetchants are used to remove material from a barrier layer from that usedto remove material from a polysilicon layer due to differences in etchselectivity. For example, in some embodiments, a chlorine-containingetchant is used to remove material from polysilicon layers; and afluorine-containing etchant is used to remove material from barrierlayers. In some embodiments, a material removal process other thanetching, e.g., laser drilling, is used for operation 450.

In operation 460, additional processes are used to complete formation ofgate structures or resistor structures. Operation 460 is similar tooperation 160; and the discussion above for operation 160 is applicablefor operation 460.

In some embodiments, method 400 includes additional operations. Forexample, in some embodiments, method 400 includes an operation forremoving a top most barrier layer over a top most polysilicon layer. Insome embodiments, an order of operations is adjusted. For example, insome embodiments, operation 430 is performed prior to operation 420. Insome embodiments, at least one operation of method 400 is omitted. Forexample, in some embodiments, operation 420 is omitted and a singledoping process is performed during operation 160.

FIGS. 5A-5D are cross-sectional views of a semiconductor device atvarious stages of manufacturing according to some embodiments. Samereference numbers correspond to same elements in each of the Figures.FIG. 5A is a cross-sectional view of a semiconductor device 500following deposition of polysilicon layer 520 according to someembodiments. Polysilicon layer 520 is on substrate 210. In someembodiments, a dielectric layer, such as an interfacial layer, a gatedielectric, an isolation structure or another suitable dielectric layer,is between at least a portion of polysilicon layer 520 and substrate510. A thickness of polysilicon layer 520 ranges from about 10 nm toabout 400 nm. In some embodiments, polysilicon layer 520 is doped.

FIG. 5B is a cross-sectional view of semiconductor device 200′ followingformation of barrier layer 530 according to some embodiments. Incomparison with semiconductor device 500, semiconductor device 500′includes barrier layer 530 over polysilicon layer 520. In someembodiments, barrier layer 530 includes silicon oxide, silicon nitride,silicon oxynitride, silicon carbide or another suitable barriermaterial. In some embodiments, barrier layer 230 a includes a samematerial as barrier layer 230 b. A thickness of barrier layer 230 issubstantially constant. In some embodiments, a thickness of the barrierlayer ranges from about 0.3 nm to about 5 nm. As a thickness of thebarrier layer increases, a resistance in the polysilicon structureincreases. If a thickness of the barrier layer is too small, the barrierlayer will not be able to inhibit increases in grain size in thepolysilicon material.

FIG. 5C is a cross-sectional view of semiconductor device 500″ afterdeposition of a second polysilicon layer 540 according to someembodiments. In comparison with semiconductor device 500′, semiconductordevice 500″ includes polysilicon layer 540 over barrier layer 530. Athickness of polysilicon layer 540 ranges from about 10 nm to about 400nm. In some embodiments, polysilicon layer 540 has a same thickness aspolysilicon layer 520. In some embodiments, polysilicon layer 540 has adifferent thickness from polysilicon layer 520. In some embodiments,polysilicon layer 540 is deposited using a same process as that used forpolysilicon layer 520. In some embodiments, polysilicon layer 540 isdeposited using a different process from that used for polysilicon layer520. In some embodiments, polysilicon layer 540 is doped.

FIG. 5D is a cross-sectional view of semiconductor device 200* followingpatterning of the polysilicon layers 520 and 540 and barrier layer 530according to some embodiments. In comparison with semiconductor device500″, semiconductor device 500* includes gate structures 550 a and 550b. Polysilicon structure 520 a; barrier layer 530 a and polysiliconstructure 540 a are part of a gate structure 250 a. Polysiliconstructure 520 b; barrier layer 530 b and polysilicon structure 540 b arepart of a gate structure 250 b. Gate structures 550 a and 520 b areformed by removing portions of polysilicon layer 520; barrier layer 530and polysilicon layer 540, such as by using a lithography and etchingprocess.

In some embodiments, a portion of substrate 510 below gate structure 550a has a different dopant type from a portion of substrate 510 below gatestructure 550 b. In some embodiments, an isolation feature, such as ashallow trench isolation (STI), is in substrate 510 below gate structure550 a or gate structure 550 b. Semiconductor device 500* includes twogate structures 550 a and 550 b. In some embodiments, semiconductordevice 500* includes more than two gate structures.

FIG. 6 is a cross-sectional view of a gate structure 600 according tosome embodiments. Gate structure 600 includes polysilicon structures 610a, 610 b, 610 c and 610 d, collectively referred to as polysiliconstructures 610. Gate structure 600 further includes barrier layers 620a, 620 b and 620 c, collectively referred to as barrier layers 620.While gate structure 600 includes three barrier layers, in someembodiments, a number of barrier layers in gate structure 600 rangesfrom 1 to about 10. Barrier layers 620 independently have a dielectricconstant ranging from about 2 to about 13. Barrier layer 620 a isbetween polysilicon structure 610 a and polysilicon structure 610 b.Barrier layer 620 b is between polysilicon structure 610 b andpolysilicon structure 610 c. Barrier layer 620 c is between polysiliconstructure 610 c and polysilicon structures 610 d. A grain size inpolysilicon structure 610 a is greater than a grain size in polysiliconstructure 610 b. A grain size in polysilicon structure 610 b is greaterthan a grain size in polysilicon structure 610 c. A grain size of inpolysilicon structure 610 c is greater than a grain size in polysiliconstructure 610 d. The larger grain sizes are the result of the lowerpolysilicon structures 610 being subjected to a greater number ofthermal processes.

A thickness Hb of the barrier layers 620 is substantially constantacross gate structure 600. In some embodiments, thickness Hb of thebarrier layers 320 independently ranges from about 0.3 nm to about 5 nm.As a thickness of the barrier layers 620 increase, a resistance in thegate structure 600 increases. If a thickness of the barrier layers 620is too small, the barrier layers will not be able to inhibit increasesin grain size in the polysilicon structures 610.

A thickness Hp of polysilicon structures 610 independently ranges fromabout 10 nm to about 400 nm. In some embodiments, at least one ofpolysilicon structures 610 is doped. The thickness Hp of polysiliconstructures 610 is determined based on a technology node of thesemiconductor device containing gate structure 600. A gate height Hg ofgate structure 600 ranges from about 15 nm to about 410 nm. The gateheight Hg of gate structure 600 is determined based on a technology nodeof the semiconductor device containing gate structure 600.

FIG. 7 is a cross-sectional view of a gate structure 700 according tosome embodiments. Gate structure 700 includes polysilicon structures 710a and 710 b, collectively referred to as polysilicon structures 710.Gate structure 700 further includes barrier layer 720. Barrier layer 720is between polysilicon structure 710 a and polysilicon structure 710 b.A grain size in polysilicon structure 710 a is greater than a grain sizein polysilicon structure 710 b. The larger grain sizes are the result ofthe lower polysilicon structures 710 being subjected to a greater numberof thermal processes. Gate structure 700 also includes dopants 730.

Dopants 730 are located along grain boundaries in polysilicon structures710. Dopants 730 are also present in barrier layer 720. In someembodiments, dopants 730 are driven into barrier layer 720 during anannealing process to active the dopants. In some embodiments, dopants730 are implanted into barrier layer 720.

In comparison with other approaches, maintaining smaller grain sizes inpolysilicon structures 710 helps to create numerous conductive pathsthrough gate structure 700. As a number of conductive paths in gatestructure 700 increase, the resistance of gate structure 700 decreases.The smaller grain boundaries also result in a more even distribution ofdopants 730 in gate structure 700 as compared to other approaches. Theeven distribution helps to increase predictability of performance ofgate structure 700 in relation with other gate structures in a samesemiconductor device. The increased predictability of performanceincreases precision in data retrieval in memory devices which includebarrier layer 720; and reduce overdesign of batteries for devices whichinclude barrier layer 720.

While barrier layer 720 is depicted as having a substantially constantthickness, similar to barrier layers 620 (FIG. 6 ); the above discussionabout dopants 730 is also applicable to barrier layers having varyingthicknesses, such as barrier layers 320 (FIG. 3 ).

An aspect of this description relates to a semiconductor device. Thesemiconductor device includes a first polysilicon structure, wherein thefirst polysilicon structure has a first grain size. The semiconductordevice further includes a first barrier layer over the first polysiliconstructure, wherein the first barrier layer has a non-uniform thickness.The semiconductor device includes a second polysilicon structure overthe first barrier layer, wherein the second polysilicon structure has asecond grain size different from the first grain size. In someembodiments, the second grain size is smaller than the first grain size.In some embodiments, the first barrier layer includes a central region;and a peripheral region, wherein the peripheral region is closer to anedge of the semiconductor device than the centration region, and theperipheral region has the non-uniform thickness. In some embodiments, athickness of the peripheral region increases as a distance from the edgeof the semiconductor device decreases. In some embodiments, the centralregion has a uniform thickness. In some embodiments, the semiconductordevice includes dopants in each of the first polysilicon structure andthe second polysilicon structure. In some embodiments, a uniformity ofdistribution of the dopants in the first polysilicon structure isdifferent from a uniformity of distribution of the dopants in the secondpoly silicon structure. In some embodiments, the dopants are in thefirst barrier layer. In some embodiments, the dopants are along grainboundaries in the first polysilicon structure.

An aspect of this description relates to a semiconductor device. Thesemiconductor device includes a first polysilicon structure. Thesemiconductor device includes a second polysilicon structure over thefirst polysilicon structure. The semiconductor device includes dopantsin each of the first polysilicon structure, wherein a uniformity of adistribution of dopants in the first polysilicon structure is differentfrom a uniformity of a distribution of dopants in the second polysiliconstructure. In some embodiments, the semiconductor device includes afirst barrier layer between the first poly silicon structure and thesecond polysilicon structure. In some embodiments, the first barrierlayer has a uniform thickness. In some embodiments, the first barrierlayer has a non-uniform thickness. In some embodiments, the dopants arein the first barrier layer. In some embodiments, the first polysiliconstructure has a first grain size, the second polysilicon structure has asecond grain size different from the first grain size.

An aspect of this description relates to a method of making asemiconductor device. The method includes forming a barrier layer over afirst polysilicon layer. The method includes depositing a secondpolysilicon layer over the barrier layer. The method includes increasinga grain size of the first polysilicon layer simultaneously withdepositing the second polysilicon layer. In some embodiments, formingthe barrier layer comprises forming the barrier layer having a uniformthickness. In some embodiments, forming the barrier layer comprisesforming the barrier layer having a non-uniform thickness. In someembodiments, the method further includes doping the first polysiliconlayer and the second poly silicon layer. In some embodiments, the methodfurther includes doping the barrier layer.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A semiconductor device comprising: a first polysilicon structure, wherein the first polysilicon structure has a first grain size; a first barrier layer over the first polysilicon structure, wherein the first barrier layer has a non-uniform thickness; and a second polysilicon structure over the first barrier layer, wherein the second polysilicon structure has a second grain size different from the first grain size.
 2. The semiconductor device of claim 1, wherein the second grain size is smaller than the first grain size.
 3. The semiconductor device of claim 1, wherein the first barrier layer comprises: a central region; and a peripheral region, wherein the peripheral region is closer to an edge of the semiconductor device than the centration region, and the peripheral region has the non-uniform thickness.
 4. The semiconductor device of claim 3, wherein a thickness of the peripheral region increases as a distance from the edge of the semiconductor device decreases.
 5. The semiconductor device of claim 3, wherein the central region has a uniform thickness.
 6. The semiconductor device of claim 1, further comprising dopants in each of the first polysilicon structure and the second polysilicon structure.
 7. The semiconductor device of claim 6, wherein a uniformity of distribution of the dopants in the first polysilicon structure is different from a uniformity of distribution of the dopants in the second poly silicon structure.
 8. The semiconductor device of claim 6, wherein the dopants are in the first barrier layer.
 9. The semiconductor device of claim 6, wherein the dopants are along grain boundaries in the first polysilicon structure.
 10. A semiconductor device comprising: a first polysilicon structure; a second polysilicon structure over the first polysilicon structure; and dopants in each of the first polysilicon structure, wherein a uniformity of a distribution of dopants in the first polysilicon structure is different from a uniformity of a distribution of dopants in the second polysilicon structure.
 11. The semiconductor device of claim 10, further comprising a first barrier layer between the first polysilicon structure and the second polysilicon structure.
 12. The semiconductor device of claim 11, wherein the first barrier layer has a uniform thickness.
 13. The semiconductor device of claim 11, wherein the first barrier layer has a non-uniform thickness.
 14. The semiconductor device of claim 11, wherein the dopants are in the first barrier layer.
 15. The semiconductor device of claim 10, wherein the first polysilicon structure has a first grain size, the second polysilicon structure has a second grain size different from the first grain size.
 16. A method of making a semiconductor device, the method comprising: forming a barrier layer over a first polysilicon layer; depositing a second polysilicon layer over the barrier layer; and increasing a grain size of the first polysilicon layer simultaneously with depositing the second polysilicon layer.
 17. The method of claim 17, wherein forming the barrier layer comprises forming the barrier layer having a uniform thickness.
 18. The method of claim 17, wherein forming the barrier layer comprises forming the barrier layer having a non-uniform thickness.
 19. The method of claim 17, further comprises doping the first polysilicon layer and the second poly silicon layer.
 20. The method of claim 19, further comprising doping the barrier layer. 